Cortex-R5 builds on the feature set of Cortex-R4 with enhanced error management, extended functional safety, and SoC integration features that suit it for use in deeply embedded real-time and safety-critical automotive, … Then go to the arm website and find the ARM ARM for that family and find the TRM (technical reference manual) for the specific core including revision if the vendor has supplied that (r2p0 means revision 2.0 (two point zero, 2p0)), even if there is a newer rev, use the manual that goes with the one the vendor used in their design. The ARM Cortex-R is a family of 32-bit RISC ARM processor cores licensed by Arm Holdings.The cores are optimized for hard real-time and safety-critical applications. Dual-core ARM® Cortex™-A53 MPCore™ up to 1.3GHz Real-Time Processor Graphics Processor Video Codec Programmable Logic Dual-core ARM Cortex-R5 MPCore up to 533MHz 103K –600K System Logic Cells Applications Quad-core ARM Cortex-A53 MPCore up to 1.5GHz Dual-core ARM Cortex-R5 MPCore up to 600MHz 1143K System Logic Cells Mali™-400 MP2 This book is for Cortex-R5 processors. In the processor the same register set is used in both the ARM and Thumb states. For automotive applications, Cortex-R5 processors offer features that are suitable for a wide range of automotive applications. Getting Started The Arm Cortex-R5 processor forms a simple migration path from the Cortex-R4 processor, and onwards to the higher performance Cortex-R8 and Cortex-R52 processors. • ARM® AMBA® APB Protocol Specification v2.0 (ARM IHI 0024). Cortex-R5’s high-performance, real-time deterministic control is well suited for vehicle electrification applications including the traction motor and inverter controller or for battery management and charging.

EG devices feature a quad-core ARM® Cortex-A53 platform running up to 1.5GHz. The Technical Reference Manual (TRM) describes the functionality and the effects of functional options on the behavior of the Cortex-R5 processor. See the ARM Cortex-R5 Technical Reference Man-ual and ARM Cortex-R5 Configuration and Sign-off Guide for more information about the con-figurations supported by ARM. ... Cortex-R5 Technical Reference Manual Programmers Model Exceptions Cortex-R5 Technical Reference Manual .
Cortex-R5 Technical Reference Manual: Revision: r1p2: Home > Level One Memory System > About the caches: 8.5. The Cortex-R5 model is available with a limited co nfiguration, including a predefined subset of the ARM Cortex-R5 configuration choices. pn Identifies the minor revision or modification status of the product, for example, p2. The Cortex-R4 core was commonly used in high-volume, deeply embedded SoC applications such as hard-disk drive controllers, wireless baseband processors, consumer products, and electronic control units for automotive systems. This would require two copies of the memories to be placed too, to allow for "split" operation. 2 Confidential 3 ARM Architecture profiles §Application profile (ARMv7 -A àe.g. Cortex -A8) §Memory management support (MMU) §Highest performance at low power §Influenced by multi-tasking OS system requirements §TrustZone and Jazelle-RCT for a safe, extensible system §Real-time profile (ARMv7 -R àe.g. High performance Arm Cortex-R-based MCUs from 80 Mhz up to 330 MHz with intelligent peripherals to offload the CPU. For a full architectural description of the MPU, see the ARM Architecture Reference Manual. ... Cortex-R5 Technical Reference Manual Programmers Model Exceptions Cortex-R5 Technical Reference Manual . • ARM ® CoreSight™ Technology System Design Guide (ARM DGI 0012). An overview of the ARM Cortex-R5 core The Cortex-R series of cores from ARM focus on real-time applications. • ARM® CoreSight™ Components Technical Reference Manual (ARM DDI 0314). Developer Documentation. light theme enabled. Developer Documentation. Thumb state The processor executes 32-bit and 16-bit halfword-aligned Thumb instructions in this state. The L1 memory system can be configured to include instruction and data caches of varying sizes.