Instruction Formats: Instruction formats: all 32 bits wide (one word): ... 16. addition immediate without overflow: addiu instruction Identical as addi instruction, except: - op-code=9 dec - overflow ignored 3. Both addi and addiu sign extend their constant field, even though addiu is considered an “unsigned” operation. MIPS provides two versions of the main arithmetic instructions. 二、格式不同. Mips instruction set has a variety of operational code AKA opcodes.These opcodes are used to perform different types of task such as addition, subtraction, multiplication of signed or unsigned numbers. —But addu, addiu, and subu do not raise exceptions on overflow Be careful! 1、add：add的格式为add $寄存器里的数,...$寄存器里的数 。 addiu at, at, 0xE520 It looks to me like that should add up to 0x896E520, but it actually adds up to 0x895E520.-----I did some tests in PPSSPP. MIPS Instructions Note: You can have this handout on both exams. —The add, addi and sub instructions will raise an exception if they cause an overflow. addi and addiu sign-extend their 16-bit immediate to 32 bits (so can represent signed 2's complement values from -32768 .. 32767, i.e. MIPS opcode (3 1 :26) jai beq bne blez bgtz addi addiu s Iti sltiu andi ori xori (2) 1b IWI Ibu Lwr SWI swr cache 11 lwcl IWC2 pref Ldcl Idc2 sc swcl swc2 sdcl sdc2 1 MIPS funct (5:0) sr1 s ra s 11 v srlv s rav jalr movz movn syscall break sync mfhi mthi mflo mtlo mult multu div divu add addu sub subu and or xor nor s It sltu t ge tgeu t It t 1 tu 1、add：add是寄存器里的数相加。 2、addi：addi是输入数与寄 1653 存器的数相加。. MIPS Stands for Microprocessor without Interlocked Pipeline Stages. unsigned values of 0..0x7fff and 0xffff8000 .. 0xffffffff) Bitwise boolean logical instructions like andi, ori, and xori … MIPS instruction set is a Reduced Instruction Set Computer ISA(Instruction Set Architecture). 17. 一、相加不同. Instruction Opcode/Function Syntax Operation trap : 011010: o i: Dependent on OS; different values for immed26 specify different operations. MIPS指令集中的 2113 add与addi区别为： 相加 不同 5261 、格式不 同、 溢出不同。 4102. CS2504, Spring'2007 ©Dimitris Nikolopoulos 14 MIPS Assembly add, addi, sub may cause exceptions on overflow addu, addiu, subu do not cause exceptions on overflow MIPS throws an interrupt upon overflow Asynchronous and unscheduled procedure call Jump to predefined address (e.g. set by the OS) Recoverable or non-recoverable EPC holds PC of instructions triggering the exception Implementation of a 32-bit MIPS processor that executes addi, addiu, bne, sw - t17711/mips-32-bit-processor